Regviz

Silicon Labs /EFR32MG24A020F1536GM48 /RAC_S /DIGCLKRETIMECTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DIGCLKRETIMECTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C112F352GM32/RAC_S/DIGCLKRETIMECTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)DIGCLKRETIMEENRETIME 0 (enable_retime)DIGCLKRETIMEDISRETIME 0 (reset)DIGCLKRETIMERESETN 0DIGCLKRETIMELIMITH 0DIGCLKRETIMELIMITL

DIGCLKRETIMERESETN=reset, DIGCLKRETIMEENRETIME=disable, DIGCLKRETIMEDISRETIME=enable_retime

Description

No Description

Fields

DIGCLKRETIMEENRETIME

DIGCLKRETIMEENRETIME

0 (disable): undefined

1 (enable): undefined
DIGCLKRETIMEDISRETIME

DIGCLKRETIMEDISRETIME

0 (enable_retime): undefined

1 (disable_retime): undefined
DIGCLKRETIMERESETN

DIGCLKRETIMERESETN

0 (reset): undefined

1 (operate): undefined
DIGCLKRETIMELIMITH

DIGCLKRETIMELIMITH
DIGCLKRETIMELIMITL

DIGCLKRETIMELIMITL

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data